The present invention relates generally to semiconductor device structures, and, more particularly, to on-chip inductor's shielding structures.
Modern analog circuits increasingly embed inductors on the chip. FIG. 1A illustrates an on-chip spiral inductor 100, which is formed by a spiral metal line 106. A first terminal 102 of the inductor 100 is on the same metal layer of the spiral metal line 106. A second terminal 104 is connected to an end of the spiral metal line 106 through vias 120 and a metal line 110 on another metal layer. FIG. 1B is a cross-sectional view of the on-chip spiral inductor 100 at a location A-A′. The inductor 100 is formed inside a dielectric material 130 on top of a semiconductor substrate 140.
Performance of these analog circuits depends heavily on the quality of the inductor, where poor inductor quality factor (Q) of silicon processes leads to degradation in circuit efficacy, especially at radio frequency (RF) and microwave frequencies. The inductor quality factor (Q) is defined as:
                    Q        =                  2          ⁢                                          ⁢                      π            ·                                          energy                -                stored                                            energy                -                loss                -                in                -                one                -                oscillation                -                circle                                                                        (        1        )            The inductor Q degrades at high frequencies due to energy dissipation in the semiconductor substrate. Noise coupling via the substrate at gigahertz frequencies has also been reported. As inductors occupy substantial chip area, they can potentially be the source and receptor of detrimental noise coupling. Therefore, decoupling the inductor from the surrounding materials, including the substrate, can enhance the overall performance of the inductor: increase Q, improve isolation, and simplify modeling.
FIG. 2 is a cross-sectional view of a patterned-ground-shielding (PGS) 203 traditionally used to provide the decoupling of the inductor 100 from the semiconductor substrate 140. The PGS 203 is commonly inserted between the inductor 100 and the substrate 140, and formed by either a polysilicon layer or a metal layer. However, it is often difficult to find optimized widths and spacings for the PGS 203 to achieve maximum Q improvement. The fact that the PGS 203 is formed inside the dielectric layer 130 also limits its effectiveness in improving the Q of the inductor 100.
As such, what is desired are alternative shielding structures for on-chip inductors that may benefit from new semiconductor processes, and these alternative shielding structures are often augmentative to traditional shielding structures.